There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low pulse occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by the various DRAM manufacturers.
Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM) for example has an additional pin for receiving a system clock signal. Since the system clock is connected to each device in a memory system, it is highly loaded, and it is always toggling circuitry in every device. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin. Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.
It is desirable to design and manufacture a memory device having a standard DRAM pinout and a burst mode of operation where multiple data values can be sequentially written to or read from the device in response to a single address location and multiple access cycle strobes. It is also desirable that this new memory device operate at higher frequencies than standard DRAMs.
In a standard DRAM device, equalization of internal data I/O lines is performed in response to column address transitions in preparation for reading or writing data from another memory cell, and also in response to a receipt of a write command to reduce the maximum signal transition on the data lines once the write drivers are enabled. Since there is a relatively wide time period in which column addresses may become valid, it has been advantageous to use an asynchronous address transition detection circuit to generate an equilibration control signal in response to address transitions. In EDO and fast page mode devices for example, the column address is treated as valid during a page mode cycle while /CAS is high. A read cycle will begin while /CAS is high at the column address indicated by the column address input signals. However, the column address is allowed to change until /CAS falls. Any column address change during the /CAS high time will require a new equilibration of I/O lines and the selection of the new column. When /CAS falls, the column address is latched and further transitions are masked. Equilibration of I/O lines allows for faster sensing of read data, and for faster writing of input data. If the data lines are each equalized to one half of Vcc for example, then the write data drivers will only need to drive one line from half Vcc to ground, and the other from half Vcc to Vcc. Otherwise, if the write data is not equal to the data previously on the I/O lines, the write data drivers will need to drive both true and compliment I/O lines a full Vcc swing for each data bit being written. Equalization of the data I/O lines reduces the maximum write cycle time by eliminating the worst case signal swing conditions. A similar situation exists during read cycles. In a read cycle, data sense amplifiers only need to drive an equilibrated I/O line from half Vcc to Vcc or ground. If the I/O lines were not equilibrated, the sense amplifiers would need to be large enough to overcome the full data signals on the I/O lines in a read cycle in a short period of time to allow for fast data access. A simple method of equilibrating the I/O lines is to: disable I/O line drivers; isolate the I/O lines from the digit lines; and couple complimentary I/O lines together. When a true I/O line is coupled to a complimentary I/O line, a logic high will be coupled to a logic low and each line will equalize to a potential approximately half way between a high and a low. It is important to disable the I/O line drivers during equilibration to prevent a true logic driver from being coupled to a complimentary logic driver which will draw excessive current from the logic high source to the logic low source.
In a burst access memory device, each access cycle can begin at a fixed point in time relative to the access cycle strobe or clock signal. In this case, an asynchronous address detection circuit is not required since address changes can be restricted to a fixed point in time relative to the access cycle strobe.